1. Field of the Invention
The present invention relates to an output circuit with a buffer.
2. Description of the Related Art
FIG. 3 shows a prior output circuit. In the output circuit, a source follower transistor N1 and a bias transistor N2 constitute an output buffer. N4 denotes a discharge transistor whose drain is connected to an output terminal TOUT. The gate of the transistor N4 is given a periodic discharge pulse DIS for the purpose of discharging a load LD, and the gate of the transistor N2 is given a constant bias voltage Vb as shown in FIG. 4
When an input voltage VIN is applied to the gate of the transistor N1 and the constant bias voltage Vb is applied to the gate of the transistor N2, an output voltage according to the input voltage VIN is supplied to the load LD. The discharge pulse DIS is applied to the gate of the transistor N4 in synchronism with the periodic input voltage VIN. After the load Ld is discharged through the transistor N4, the load LD is charged again according to the input voltage VIN.
The above described output circuit has a problem that it takes not a little time to discharge the load LD due to the limit of the discharge capacity of the transistor N4, and to charge the load LD to a sufficient voltage level for the output circuit to output a voltage corresponding to the input voltage since the load LD is completely discharged to the ground level.